Method for forming an electronic device in multi-layer structure

ABSTRACT

A method for forming an organic or partly organic switching device, comprising: depositing layers of conducting, semiconducting and/or insulating layers by solution processing and direct printing; defining microgrooves in the multilayer structure by solid state embossing; and forming a switching device inside the microgroove.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to electronic devices, especially organicelectronic devices, and methods for forming such devices.

2. Description of the Related Art

Semiconducting conjugated polymer thin-film transistors (TFTs) haverecently become of interest for applications in cheap, logic circuitsintegrated on plastic substrates (C; Drury, et al., APL 73, 108 (1998))and optoelectronic integrated devices and pixel transistor switches inhigh-resolution active-matrix displays (H. Sirringhaus, et al., Science280, 1741 (1998), A. Dodabalapur, et al. Appl. Phys. Left. 73, 142(1998)). In test device configurations with a polymer semiconductor andinorganic metal electrodes and gate dielectric layers high-performanceTFTs have been demonstrated. Charge carrier mobilities up to 0.1 cm2Nsand ON-OFF current ratios of 106-108 have been reached, which iscomparable to the performance of amorphous silicon TFTs (H. Sirringhaus,et al.; Advances in Solid State Physics 39, 101 (1999)).

One of the advantages of polymer semiconductors is that they lendthemselves to simple and low-cost solution processing. However,fabrication of all-polymer TFT devices and integrated circuits requiresthe ability to form lateral patterns of polymer conductors,semiconductors and insulators. Various patterning technologies such asphotolithography (WO 99/10939 A2), screen printing (Z. Bao, et al.,Chem. Mat. 9, 1299 (1997)), soft lithographic stamping (J. A. Rogers,Appl. Phys. Lett. 75, 1010 (1999)) and micromoulding (J. A. Rogers,Appl. Phys. Lett. 72, 2716 (1998)), as well as direct ink-jet printing(H. Sirringhaus, et al., UK 0009911.9) have been demonstrated.

Many direct printing techniques are unable to provide the patterningresolution that is required to define the source and drain electrodes ofa TFT. In order to obtain adequate drive current and switching speedchannel lengths of less than 10 μm are required. In the case of inkjetprinting this resolution problem has been overcome by printing onto aprepatterned substrate containing regions of different surface freeenergy (H. Sirringhaus et al., UK 0009915.0).

In U.S. patent application No. 60/182,919 a method is demonstrated bywhich an inorganic metal film on top of a polymer support can bemicrocut by solid state embossing (N. Stutzmann et al., Adv. Mat. 12,557 (2000)). A “hard” master containing an array of sharp, protrudingwedges is pushed into a polymer supported metal film at elevatedtemperatures. For a semicrystalline polymer, such aspoly(tetrafluoroethylene-co-hexafluoropropylene) (FEP), polyethylene(PE), or poly(ethylene terepthalate) (PET), the embossing temperature isabove the glass transition of the polymer, but below its meltingtemperature. In the case of an amorphous polymer such as atacticpolystyrene (PS) or poly(methylmethacrylate) (PMMA) temperatures aroundthe glass transition are used. During the embossing the masterpenetrates into the metal-polymer structure and plastic flow of materialoccurs away from the wedge. If the indentation depth is larger than themetal film thickness a groove is generated which cuts through the metalfilm. In the remaining areas the integrity of the metal-polymer layerstructure is preserved because embossing is performed in the solid stateand plastic flow mainly occurs laterally.

SUMMARY OF THE INVENTION

According to the present invention there is provided methods and devicesas set out in the accompanying claims. In particular, according to oneaspect of the invention there is provided a method for forming an.electronic device in a multilayer structure comprising at least a firstlayer and a second layer, the method comprising forcing a microcuttingprotrusion of a cutting tool into the multi-layer structure so as tocause the protrusion to microcut through the first layer.

Other aspects of the invention include devices formed by that and othermethods, and integrated circuits, logic circuits, display circuitsand/or memory device circuits comprising one or more of such devices.Preferably the said devices are formed on a common substrate. Preferablythe said devices are formed in a common layer of an organic material.

Preferred aspects of the present invention relate to methods by whichsolid state embossing can be used to fabricate polymer transistordevices and circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be described by way of example, withreference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of one embodiment of the solid stateembossing and microcutting process;

FIG. 2 shows environmental scanning electron microscopy images ofmicrocut PEDOT films on different polymer supports (A/B: 800 Å PEDOT ontop of 3 μm PMMA; C/D: 800 Å PEDOT on top of 3 μm PVP). The bright areasare those covered with PEDOT;

FIG. 3 a schematic top view of a possible source-drain electrodeconfiguration to fabricate a regular array of discrete TFT devices bycombining direct printing with solid state embossing. For integratedcircuit fabrication interconnects between any two TFT devices can bedefined by direct printing, as indicated by the dashed line;

FIG. 4 shows a schematic diagram of the process sequence for fabricatinga top-gate polymer TFT by a combination of solid state embossing anddirect printing;

FIG. 5 shows a possible process sequence for fabricating a verticalpolymer TFT by solid state embossing;

FIG. 6 illustrates a method for fabricating self-aligned gate electrodesfor polymer TFTs by a combination of solid state embossing and selectivesurface modification;

FIG. 7 shows an alternative method for preparation of a surface freeenergy pattern that can be used to fabricate narrow conductinginterconnect lines and electrodes by direct inkjet printing;

FIG. 8 illustrates fabrication of a via-hole interconnect by solid stateembossing;

FIG. 9 shows another schematic diagram of a multilayer structure forfabrication of vertical transistors and a photograph of a completedtransistor with a triple layer of embossed gold/1 μm PVP/gold;

FIG. 10 shows output and transfer characteristics of a vertical,embossed polymer transistor measured with electrodes E2 and E3 assource-drain electrodes;

FIG. 11 shows output and transfer characteristics of a planar, embossedpolymer transistor measured with electrodes E2 and E4 as source-drainelectrodes;

FIG. 12 shows a cylindrical microcutting tool used to emboss acontinuous, flexible substrate in a reel-to-reel process;

FIG. 13 shows a light emitting diode device fabricated on a verticalside wall that also forms an optical waveguide structure;

FIG. 14 shows an electrically driven laser device with n- and p-typetransistor channels that provide electron and hole injection into thelight emitting semiconductor material;

FIG. 15 shows a device with a lateral p-n junction formed in themicrocut groove.

FIG. 16 By combining a multitude of microcutting tools comprising thesame or different relief structures large-area microcutting tools ofe.g. planar (FIG. 16 a) but also cylinder-shape (FIG. 16 b) can readilybe fabricated. Alternatively, cylinder-shaped microcutting tools canalso fabricated by bending e.g. a sheet comprising protruding edges thatare flexible enough (16 c).

DETAILED DESCRIPTION OF THE ILLUSTRATIVE NON-LIMITING EMBODIMENTS OF THEINVENTION

A first example demonstrates the application of solid state embossing tomicrocutting of conducting polymer films.

FIG. 1 shows a schematic diagram of solid state embossing of a thin filmof PEDOT/PSS on top of a thick, smooth insulating polymer support suchas PMMA, poly(vinylphenol) (PVP), poly(styrene) (PS) or polyimide (PI).The insulating polymer film is deposited on top of the 7059 glasssubstrate by spin coating from a 15-30 weight % solution in propyleneglycol methyl ether acetate (PVP) and cyclopentanone (PMMA),respectively, resulting in a film thickness of 2-3 μm. Prior to thedeposition of the PEDOT the surface of the insulating polymer isrendered hydrophilic by O₂ plasma treatment in order to promote theadhesion of the PEDOT film. A 800 Å film of PEDOT/PSS (Baytron P fromBayer corporation) is then spincoated from a water dispersion. Embossingis performed at a temperature of 150° C. (PVP), 100° C. (PS), 105° C.(PMMA) for up to 60 min with a load of about 1 kg/mm². Other processingconditions have also been shown to yield satisfactory results.Subsequently, the sample is cooled to room temperature before thepressure and the master are removed.

Critical in the method according to the present invention, is thatduring the microstructuring process the polymer substrate 3 is in itssolid state. Accordingly, for amorphous polymers the method is carriedout around the glass transition temperature, T_(g). The lattertemperatures generally are well known and can be found for instance inPolymer Handbook (Eds., J. Brandrup, H. Immergut, E. A. Grulke, JohnWiley & Sons., New York, 1999), or can readily be determined accordingto standard thermal analysis methods. Preferably, the microstructuringprocess according to the present invention is carried out in atemperature range from about 50° C. below to about 50° C. above T_(g)and more preferably from about 40° C. below to about 40° C. above thattransition. Most preferred is the temperature range from about 25° C.below to about 25° C. above T_(g). For semi-crystalline polymers themicrostructuring method according to the present invention is carriedout in the temperature regime between about the glass transitiontemperature, T_(g). and the melting temperature, T_(m). The lattertemperatures generally are also well known and can also be found forinstance in Polymer Handbook, or can readily be determined according tostandard thermal analysis methods. Preferably, the microstructuringprocess is carried out in a temperature range from about 50° C. belowT_(g) to 1° C. below T_(m), and more preferably from about 25° C. belowT_(g) to 2° C. below T_(m). Most preferred is the temperature range fromT_(g) to about 5° C. below T_(m). Other processing parameters, such asthe load that is applied onto the master and time period during which itis applied, are less critical and are readily adjusted to ensure thatthe desired penetration of the master through one or more of the layers2 a is effected.

One of the other important features of the process is that the master orthe substrate to be embossed can be in contact with a soft rubberymaterial through which the pressure during the embossing is transmittedin a homogeneous way, such that a homogeneous depth of microgrooves isobtained across the substrate.

It should be noted that a conducting polymer film such aspoly(3,4-ethylenedioxythiophene) protonated with polystyrene sulfonicacid (PEDOT/PSS) has very different mechanical and elastic, as well asadhesive properties than a hard, polycrystalline film of an inorganicmetal such as gold or silver. Therefore, techniques for processing hardfilms are not generally extensible to polymer film processing.

FIG. 2 shows environmental scanning electron microscopy (ESEM) images ofa microcut PEDOT film on PMMA. The silicon master in this case consistsof a parallel array of sharp wedge-shaped protrusions. The lateral sizeof the microcut grooves, i.e., the separation gap between the PEDOTelectrodes, is determined by the shape of the wedge and the indentationdepth. We have fabricated patterns of parallel stripes of PEDOTseparated by microgrooves with gaps down to 0.6 μm and indentationdepths of about 1.5 μm using a wedge with an opening angle α of 70°(FIG. 2).

In some cases it was found that only every second line had been microcut(see FIG. 2D). In some circumstances this might be acceptable, but if itis to be avoided it has been found helpful to promote the adhesion ofthe PEDOT layer to the underlying polymer support, for example by makinguse of adhesion promoters or plasma treatment of the polymer supportprior to deposition of the PEDOT.

Another example demonstrates a method by which solid-state embossing canbe combined with direct printing to define all-polymer transistordevices and integrated TFT circuits. We use microcutting of conductingpolymer films to accurately define the active channel region between thesource and drain electrodes of the TFT with submicrometer resolution. Wecombine solid state embossing with direct printing techniques such asinkjet printing or screen printing. This allows us to fabricate discreteTFT devices and arbitrary integrated circuits, with areas in betweendevices that do not contain conducting material. Note that microcuttingin combination with thin film deposition techniques such as evaporation,spin-coating or blade coating is capable only of removing conductingmaterial in small areas. The following features are significant:

-   -   Combination of microcutting with direct printing: To define        conducting coarse patterns on the substrate prior to embossing a        broad variety of printing techniques may be used. Conducting        polymer electrodes may be deposited directly by techniques such        as inkjet, or screen printing or micromoulding techniques. In        order to increase the electrical conductivity of the electrodes        it is possible to use the printed conducting polymer pattern as        a template for the subsequent electrodeposition of an inorganic        metal. In this case a double layer of conducting polymer and        inorganic metal film is microcut. Alternatively, a layer may be        printed (by inkjet or microcontact printing, for example) that        can subsequently be used to initiate electroless plating of a        conducting layer (H. Kind, et al., Langmuir 2000, 6367 (2000)).        Yet another possibility is the direct printing of a        solution-processible precursor to a conducting layer such as an        organometallic compound or a colloidal suspension of conducting        particles (Kydd, et al., WO 98/37133).    -   In a second step the electrode pattern is then microcut by solid        state embossing to define the small source (S)—drain (D)        separation. FIG. 3 shows a possible structure in which an array        of simple rectangular electrode patterns and interconnect lines        is deposited by direct printing, which is then embossed with a        master containing wedges that define interdigitated source-drain        electrodes. Interdigitated electrodes are advantageous since        they allow formation of TFTs with large channel width over a        small area. Arbitrary and more complex source-drain electrode        patterns can be fabricated in this way.    -   Registration: In principle, the embossed channel has to be        aligned accurately with respect to the previously deposited        coarse electrode pattern. This may be achieved by performing the        embossing step in a mask aligner with optical positioning.        However, registration issues can be largely overcome by defining        periodic TFT arrays such as the one shown in FIG. 3 in which the        master and the coarse electrode pattern are periodic in one or        two directions. In this case alignment requirements are less        critical. To fabricate integrated TFT circuits the individual        TFTs of the array can be connected by printed interconnect lines        and via-hole interconnects (see below).    -   Electrical and structural integrity: In order to avoid damage to        the TFT layers, in particular to the insulating gate dielectric,        by the embossing step, we choose a top-gate TFT structure in        which the TFT layers are formed on top of and after the embossed        source-drain pattern. As shown in FIG. 4 thin layers of the        semiconducting polymer and the gate insulating polymer are        deposited from solution followed by direct printing of a        conducting polymer gate electrode (G). For conjugated polymers        with a low bulk conductivity patterning of the semiconducting        polymer layer is not required. The formation of this layer        structure requires careful choice of solvents in order to avoid        dissolution and swelling of underlying layers. However, it has        been shown that adequate structural integrity of the different        polymer-polymer interfaces of the TFT can be achieved using an        alternating sequence of polar and non-polar solvents (H.        Sirringhaus et al., UK 0009911.9). One possible sequence of        materials is indicated in FIG. 4.    -   Structural self-organisation: In order to obtain a high charge        carrier mobility the semiconducting polymer layer needs to be        highly ordered which can be achieved by making use of        self-organisation mechanisms. Various self-organising        semiconducting polymers can be used such as regioregular        poly-3-hexylthiophene (P3HT), and polyfluorene co-polymers such        as poly-9,9′-dioctylfluorene-co-dithiophene (F8T2). In devices        such as that in FIG. 4 the channel is formed within the embossed        microgrooves. The topographic profile of the groove may be used        to induce alignment of the semiconducting polymer. Double        embossing may also be used. The polymer support can be embossed        once prior to deposition of the PEDOT S/D layer in order to        define microgrooves in the polymer support parallel to the TFT        channel. Since embossing is performed in the solid state, this        relief is maintained during the second orthogonal embossing step        to define the channel (N. Stutzmann et al., Adv. Mat. 12, 557        (2000)). If a liquid-crystalline semiconducting polymer such as        F8T2 is used (H. Sirringhaus et al., Appl. Phys. Lett. 77, 406        (2000), alignment of the polymer chains predominantly parallel        to the TFT channel can be induced using the first embossing        pattern as an alignment layer (J. Wang, et al., Appl. Phys.        Lett. 77, 166 (2000)).

Another example demonstrates a method to define vertical side walls inpolymer multilayer structures, which can be used to fabricate verticalpolymer TFT devices.

In a vertical TFT (see for example, A. Saitoh, et al. Jpn. J. Appl.Phys. 36, 668, (1997)) the channel length is defined by the thickness ofone of the deposited layers as opposed to a high-resolution patterningstep in the case of a planar TFT. In one possible configuration amesa-type structure is deposited first consisting of source and drainelectrode layers separated by a thin dielectric layer the thickness ofwhich determines the channel length of the TFT. A vertical side wall isthen formed by appropriate means such as a chemical etching process.Semiconducting and insulating layers are deposited onto the side wallsfollowed by a gate electrode. Vertical TFTs have been fabricated usinginorganic materials. They are useful because they allow formation ofsubmicrometer channel lengths without requiring expensive lithographictools, but offering enhanced circuit speed and drive currents.

Vertical polymer TFTs have not hitherto been demonstrated, because ofthe difficulties associated with forming vertical sidewalls andconformal solution coating of polymer layers onto a truly vertical sidewall. Chemical etching methods for forming side walls pose problemsbecause of the high solubility of polymers in common organic solventsand the lack of anisotropic etching mechanisms that in the case ofinorganic semiconductors cause etching to proceed faster in onecrystallographic direction that in others allowing formation of welldefined facets. More directional, physical etching methods such asreactive ion etching suffer from degradation of electrically functionalpolymers upon plasma exposure.

Solid state embossing provides a new method to overcome these polymerspecific difficulties and define side walls in a well controlled way.FIG. 5 shows the structure of a vertical polymer TFT in which thechannel is formed on the pseudo vertical inclined side wall of anembossed microgroove. The initial layer structure consists of twoconducting polymer layers that have been coarse-patterned by directprinting separated by an insulating polymer layer such as a layer PI orPVP. The insulating layer can be deposited by spin coating. Thethickness of the insulating spacer layer should be less than 2 μm,preferably less than 1 μm, most preferably less than 0.5 μm. The minimumthickness, i.e. channel length that can be achieved in this way, islimited by frictional forces between the master and the polymer layers.Friction tends to cause a downward movement of the lips of the upperconducting polymer layer during embossing. This may cause electricalshorts between the two conducting polymer layers if the thickness of thespacer layer is too small. Friction can be minimized by chemicalmodification of the master, such as deposition of a functionalself-assembled surface monolayer to minimize adhesion between the masterand the polymer layers or other friction-reducing lubricants. After theembossing step the device can be completed by depositing a conformallayer of semiconducting polymer and gate insulating polymer. Conformalcoating is facilitated by the finite inclination of the side wall thatis defined by the opening angle α of the master. Finally a gateelectrode pattern can be printed into the microgroove overlapping withthe side walls. With suitably defined printed source-drain patterns TFToperation may be obtained on both side walls of each microgroove.

Vertical transistors according to one embodiment of the presentinvention were fabricated in the following way: First, amorphouspolyethylene terephthalate, PET, films (thickness=0.25 mm; Goodfellow)were cleaned by sonication in xylene (Aldrich) and subsequentoxygen-plasma treatment for 60 sec at 50 Watt. Then, pre-structured goldpads of 1×5 mm size and a thickness of 40 nm were thermally evaporatedutilizing a suitable shadow mask. Spin-coating a 10 wt %poly(vinylphenol), PVP (M_(w)≈20 kg mol⁻¹, T_(g)≈151° C.; Aldrich)solution in isopropanol, IPA (Aldrich) at 2000 rpm for 60 sec yielded anapproximately 1 □m thick insulating film on top of these gold pads.Subsequently, a second set of gold pads were evaporated in the same wayas described above, however these pads were shifted slightly withrespect to the formerly produced ones to enable their addressing. Thetwo gold and the PVP layer were then microcut on the PET substrate inorder to define the source/drain electrodes by embossing the multilayersystem at 80° C. with a microcutting tool fabricated as described above,applying a nominal pressure of 1 kg mm⁻² for 30 min. For this purpose, aTribotrak pressing apparatus (DACA Instruments) was employed. Thevertical transistors were then completed by first spin-coating a 8 wt %solution of the semi-conducting polymer, poly(3-hexylthiophene), P3HT(supplied by R. A. J. Janssen, TUE Eindhoven, The Netherlands) inanhydrous xylene (Romil Ltd.) at 2000 rpm for 60 sec, then a 7 wt %poly(methyl methacrylate), PMMA (M_(w)≈120 kg mol⁻¹, T_(g)≈105° C.;Aldrich) solution in anhydrous butyl acetate (Romil Ltd.) also at 2000rpm and for 60 sec, and, finally, thermally evaporating another set ofgold electrodes through the same shadow mask to define the gateelectrode.

FIG. 10 shows output and transfer characteristics of such a verticalpolymer TFT fabricated by microcutting a double layer of gold electrodesseparated by a thin layer of polyvinylphenol on a PET substrate (seeFIG. 9). The semiconducting polymer layer in this example is a layer ofregioregular poly-3-hexylthiophene (P3HT) with a gate dielectric layerof PMMA deposited on top. Clean p-type accumulation operation can beobserved. Although care was taken to minimize doping of the P3HT byavoiding exposure of the P3HT to atmosphere (processing under inertnitrogen atmosphere) the device is normally on due to some residualdoping of the P3HT. However, most significantly, no shorts are observedbetween the top and bottom source-drain electrodes which is clearevidence that the microcutting technique is capable of preserving theintegrity of a multilayer stack without generating electrical shorts indifferent layers.

This opens the way to a broad range of device applications in whichmicrocutting can be used to define vertical sidewalls with electrodes indifferent layers. Examples of other useful structures with such verticalside walls are vertical light emitting diodes with anode and cathode(formed from different materials) stacked on top of each other (see FIG.13). If such a microcut groove is filled with a light emitting materialsuch as a conjugated polymer with a refractive index higher than that ofthe substrate and that of the dielectric polymer spacer layer separatinganode and cathode the light from the LED can be coupled into thewaveguide. The light might be guided within the embossed groove to someother location on the same substrate where it might be detected by avertical photodetector formed by the same method as the LED. Thisprovides a simple fabrication method for integrated opticalcommunication circuits.

Another useful device that can be fabricated in this way is anelectrically driven laser. Recently electrically driven lasers based onorganic single crystals have been demonstrated (Schön et al., Science289, 599 (2000)). The device architecture is based on TFT devices formedon both sides of the organic single crystal providing injection ofelectrons and holes from opposite sides of the crystal. Waveguiding isachieved along the parallel channel of the TFTs by the high refractiveindex of the gate electrode. However the method of fabrication requiringaccurate alignment of devices on opposite sides of the crystal is notsuitable for integration. Here we propose a method for fabricating asimilar device architecture by solid state embossing that is more suitedfor integrated circuit fabrication. A schematic drawing is shown in FIG.14. The p-channel can be formed on the bottom side of the semiconductinglayer deposited into the microembossed groove, while the n-channel canbe formed on the top of the layer or vice versa. Waveguiding of theemitted light can be achieved as described above. Optical feedback thatis required for laser action can, for example, be achieved by depositingthe layer sequence onto a substrate that had previously been embossedwith grooves in a direction perpendicular to the laser waveguide.

Vertical side walls may also be used to form well-defined interfacesbetween semiconducting layers such as lateral p-n junctions as shown inFIG. 15.

Another example demonstrates a method for forming surface relieffeatures that can be used to fabricate surface free energy patterns thatdirect and confine the solution deposition of polymer patterns.

Many direct printing techniques to deposit polymer patterns suffer froma relatively low resolution that prevents the formation of fine-scalefeatures and lines with dimensions of a few micrometers. In the case ofinkjet printing, for example, the resolution is limited to 20-50 μm bythe uncontrolled spreading of inkjet droplets on the substrate andstatistical variations in flight direction. It has been shown that theresolution can be significantly enhanced by printing onto a substratethat contains a prefabricated pattern of surface free energy. In thecase of PEDOT/PSS deposited from water solution the spreading ofdroplets can be controlled by using hydrophobic repelling banks suchthat the PEDOT deposition is accurately confined to the hydrophilicsurface regions. Different techniques have been demonstrated tofabricate such a surface free energy pattern, such as photolithographicpatterning of a hydrophobic polyimide layer on top of a hydrophilicglass substrate or photopatterning of a self-assembled monolayer (H.Sirringhaus et al., UK 0009915.0).

Another technique to generate a surface free energy pattern is softlithographic stamping (see for example, Y. Xia, et al., Angew. Chem.Int. Ed. 37, 550 (1998)). Here a soft stamp containing surface relieffeatures is fabricated by pouring a solution of poly(dimethylsiloxane)(POMS) over a patterned master. After curing and peeling off the masterthe stamp is exposed to a solution of a self-assembled monolayer (SAM)and is then brought into contact with the sample surface. The SAM isselectively transferred to the sample in those regions which are indirect contact with the stamp resulting in local modification of thesurface free energy.

Solid state embossing provides an elegant, self-aligned method forconfining the deposition of material to the embossed microgrooves bymaking use of the topographic relief features generated by the embossingstep.

If a solution of material is deposited onto a substrate containingmicrogrooves the solution will be drawn into the microgrooves bycapillary forces. This provides a mechanism for the selective depositionof material in the microgrooves.

This effect can be enhanced by modifying the surface energy of thesubstrate. If the embossed sample is brought in contact with a flat softstamp that has been exposed to a self-assembled monolayer, transfer ofthe SAM only occurs in the planar surface regions, but not on the sidewalls of the microgrooves. Flat stamps can be fabricated by using thematerials and procedure developed for soft lithography, without the needfor a surface relief, i.e. a pattern on the master.

One of the attractive advantages of this technique as opposed to softlithography is that it does not require any alignment or registrationwith respect to a previously deposited pattern. It allows for example anelegant way to fabricate a self-aligned surface free energy pattern forthe printing of the gate electrode of the TFT as shown in FIG. 6. If theplanar surface regions of the gate insulating layer are modified to behydrophobic the deposition of an inkjet printed gate electrode, forexample of PEDOT/PSS in water, is confined to the microgrooves withoutspreading into the hydrophobic surface regions. This allows fabricationof a self-aligned TFT with small overlap capacitance betweensource/drain and gate electrodes. This feature is particularly useful inthe context of vertical TFTs, because the self-alignment of printed gateelectrodes provided by the topographic groove overcomes one of thegeneral problems of vertical transistor device architectures. Mostvertical transistors suffer from a large overlap between source-drainand gate electrodes due to the difficult alignment of the verticalmetallization. As a consequence of the reduction in capacitance anintegrated circuit using embossed vertical transistors will showimproved switching times and better fan-out.

One possible choice of materials for such surface patterning is to use agate insulating layer of PVP. PVP is a moderately polar polymer due tothe hydroxyl groups attached to each phenyl ring. Its surface can bemade even more hydrophilic by brief oxygen plasma exposure such that thecontact angle of water becomes less than 30°. However, PVP is notsoluble in water, and allows deposition of a PEDOT/PSS gate electrodefrom water solution without being dissolved. Its surface can be madehydrophobic by exposure to a self-assembled monolayer ofalkyltrichlorosilanes or fluorinated alkyltrichlorosilanes. Contactangles exceeding 60° can be achieved. This contact angle difference issufficient for confining deposition of inkjet deposited PEDOT/PSSdroplets from water solution to the hydrophilic surface regions.

An alternative method of surface modifying the upper part of thestructure is to use a vapour process, such as evaporation, in which thevapour is directed at an acute angle to the upper surface. This allowsthe sides of the recess to shade at least the deeper parts of the recessfrom the vapour, so that only the upper parts of the recess and the topsurface are surface treated.

An alternative method for such surface prepatterning which does not evenrequire surface modification by stamping is shown in FIG. 7. If ahydrophobic polymer layer such as poly(dioctylfluorene) (F8) is spincoated on top of a hydrophilic polymer layer such as PVP a surface freeenergy pattern is automatically formed upon embossing when thehydrophilic polymer is exposed on the side walls of the microgrooves.This method can be used in an analogous way to define fine isolated linefeatures in combination with inkjet printing, for example forfabricating high density arrays of fine interconnect lines witharbitrary patterns.

Another example demonstrates a method for the formation of via-holeinterconnects.

In order to form integrated TFT circuits using devices of the typedescribed above, it is necessary to make via hole interconnects betweenelectrodes and interconnects in different layers. Different methods tofabricate such via-holes have been demonstrated, such as local etchingof dielectric layers using ink-jet printing (H. Sirringhaus, et al.,UK0009917.6), photolithographic patterning (G. H. Gelinck et al., Appl.Phys. Lett 77, 1487 (2000)) or serial hole punching using a mechanicalstitching machine (C. J. Drury et al., WO99/10929).

Solid state embossing offers an alternative method to open such via-holeinterconnections as illustrated in FIG. 8. If the master contains anarray of sharp pyramids (N. Stutzmann et al., Adv. Mat. 12, 557 (2000))the embossing can be used to generate a small diameter pyramidalmicrocuts through a dielectric layer exposing the surface of anunderlying conducting electrode. The groove can be filled with aconducting polymer in a subsequent printing step. This process can alsobe applied to more complicated multilayer structures containingsequences of insulating and semiconducting polymer.

The size of the via-hole is defined by the size of the pyramidal wedgeand the indentation depth. Using a wedge with an opening angle of 70°via holes with dimensions of a few micrometers or even submicrometerdimensions can be fabricated. Small size of via holes is important forfabrication of high-density integrated circuits.

One of the advantages of such a process is that it allows formation of alarge number of interconnects in a parallel way, whereas techniques suchas mechanical stitching or inkjet printing are essentially serial.

In all of the above embodiments PEDOT/PSS may be replaced by anyconducting polymer that can be deposited from solution. Examples includepolyaniline or polypyrrole. However, some of the attractive features ofPEDOT/PSS are: (a) a polymeric dopant (PSS) with inherently lowdiffusivity, (b) good thermal stability and stability in air, and (c) awork function of ≈5.1 eV that is well matched to the ionisationpotential of common hole-transporting semiconducting polymers allowingfor efficient hole charge carrier injection.

The microcutting tool has microcutting protrusions on it. These suitablytake the form of sharp protruding features, such as ridges,saw-tooth-type structures, spikes, and the like. The process of themanufacturing and the material of these microcutting tools are notcritical to the microcutting process. However, the material of which thetool is made should be sufficiently hard, and the protrusionssufficiently sharp that the tool is capable of cutting through thelayers. Where the tool is to cut through an upper layer of a multi-layerstructure the height h of the features should exceed the thickness d ofthe layer or layers that are to be cut Characteristic dimensions ofthese features, such as the feature height h, preferably are in therange between 1 mm and 1 nm. More preferably these characteristicdimensions are between about 100 μm and 5 nm, and most preferablybetween 10 μm and about 10 nm. To provide suitable sharpness the radiusof curvature of the protruding edges of these features should bepreferably less than 500 nm, more preferably less than 100 nm, and mostpreferably less than 10 nm.

The sharp protruding features may be of simple geometries (e.g.line-shaped ridges) or more complex such as interdigitated features.Examples of suitable geometries include arrays of conical or pyramidalprotrusions, and arrays of linear protrusions. One useful configurationis for the protrusions to be linear and parallel to each other.

The microcutting tool suitably comprises at least one cutting edge, butpreferably a multitude of edges. The latter allows for fabrication of amultitude of devices in one single embossing/microcutting step. Theprotruding edges may all be of the same geometry or may differ from eachother. For instance, a microcutting tool according to the presentinvention may comprise arrays of line-shaped edges (c.f. schematic topview FIG. 12) with which for example pre-structuredelectrical-conductive layers on top of a polymeric substrate (FIG. 12)can be cut in one step leading to an array of electrodes e.g. for use inelectrical devices such as thin-film transistors.

In another example the microcutting master could be either planar orcylinder-shaped or could have whatever geometry is best suited for thedevice and device configuration to be fabricated as well the fabricationprocess. Cylinder-shaped microcutting tools are particularly useful asthey allow for embossing of a continuous flexible substrate in areel-to-reel process (see FIG. 12). Reel-to-reel fabrication may offerhigher throughput, and lower cost capability than a standard batchprocess. In this context it is of particular significance that theembossing is performed preferably in the solid state, in which theembossed grooves retain their shape after the embossing tool isretracted. If the embossing were performed in the liquid phase, it wouldbe necessary to reduce the substrate temperature before removing themicrocutting tool, which would be difficult to achieve with a rollingcylindrical microcutting tool. The flexible tool could be constituted bya flexible plastics structure, or could be a flexible sheet of anothermaterial, for instance a thin (e.g. 20 micron thick) sheet of silicon.

Large-area microcutting tools according to one embodiment of the presentinvention can be fabricated for instance by combining a multitude ofmicrocutting tools comprising the same or different relief structures(see FIG. 16). Cylinder-shape microcutting tools may be fabricated byfirst producing a planar tool which is subsequently rolled or bended(see FIG. 16).

Suitable masters can be made by a variety of methods known in the art,including, but not limited to anisotropic etching techniques,lithographic methods, electroplating, electroforming and the like. It ismost preferred within the scope of the present invention to applyanisotropic etching techniques to fabricate suitable features, as thesetechniques can lead to features having edges of a radius of curvature ofless than 10 nm in a most straight-forward way. In particular,anisotropic etching of single-crystalline or polycrystalline inorganicmaterials is contemplated in the scope of this invention. A mostsuitable material is, but the present invention is not limited to,single-crystalline {100} silicon, for which anisotropic etchants such assolutions of potassium hydroxide (KOH) or tetramethyl ammonium hydroxide(TMAH) in water, with or without the addition of isopropyl alcohol (IPA)can be used. Other materials different from {100} silicon andanisotropic etchants different from those listed above might be employede.g. to vary e.g. etch angles or etching rate; these will be apparent tothose ordinarily skilled in the art of microfabrication. Also, forfabricating more complex structures, such as rectangular-shaped cornersneeded for example for producing interdigitated features, anisotropicetching techniques incorporating different compensation structures mightbe applied which are designed such that corners are protected by a“sacrificial” beam or similar structure until the desired etch depth isreached. These etching-techniques are also well-known (cf. van Kampen,R. P. and Woffenbuttel, R. F. J. Micromech. Microeng. 5, 91 (1995),Scheibe, C. and Obermeier, E. J. Micromech. Microeng. 5, 109 (1995),Enoksson, P. J. Micromech. Microeng. 7, 141 (1997)).

Anisotropic etching of silicon can suitably be used to produce a die foruse as a tool or master having protrusions whose faces correspond to the{111} faces of silicon. The angle between those faces is 70° (or moreprecisely, 70.53°). The thickness of the silicon sh et is suitablyaround 300 microns. Other materials that can be anisotropicallyetched—suitably other semiconductive materials—could be used.

Microcutting tools may be fabricated by first producing sharp featuresin e.g. a silicon waver by anisotropic etching techniques. Thatmicroshaped wafer may be used as the tool itself, or subsequentlyreplicas of that wafer may be made for use as the tool. If the wafer isshaped as a negative of the desired tool then the tool may be moulded onthe wafer. If the wafer is a positive version of the desired tool then afirst replica of the wafer may be made, and then the tool may be formedas a replica of that first replica. The replicas are suitably made inmaterials such as thermoplastic and thermosetting polymers. This has theadvantage that sharp grooves can be etched into the original master,e.g. a silicon waver, what is often a more straight-forward process thanetching sharp ridges. The polymeric replicas of such an original mastershould be sufficiently hard and capable of cutting through the layers tobe structured. Accordingly, polymers used for replica productionpreferably have a glass transition temperature larger than 25° C., morepreferably larger than 110° C. and most preferably larger than 150° C.The latter temperatures generally are well known and can be found forinstance in Polymer Handbook (Eds., J. Brandrup, H. Immergut, E. A.Grulke, John Wiley & Sons., New York, 1999). Preferably, high-glasstransition, thermosetting resins are used for producing replicatedmicrocutting tools, such as cyanate ester resins (e.g.4,4′ethylidenediphenyl dicyanate andoligo(e-methylen-1,5-phenylencyanate) or epoxy resins such astetrafunctional tetraglycidyl diaminodiphenylmethane). The latter may bemixed before with an aromatic hardener such as 4,4′-diamino diphenylsulfone, DDS. In order to fabricate replicas, a polymer melt, solutionor pre-polymeric liquid as those listed above is cast, injection- orreaction moulded, and solidified in contact with the master structure bye.g. cooling, thermally or photochemically crosslinking. The originalmaster surfaces may be rendered non-adhesive, e.g. by rendering ithydrophobic, using suitable surface treatments such as chemicallymodification with self-assembling monolayers (e.g. silylation fromvapour phase using e.g. octadecyltrichlorosilane,perfluorodecyltrichlorosilane and allyltrimethoxysilane). Alternatively,release coatings or agents such as silicon oil may be employed on thesurface of the original master. It may also be useful to apply suchcoatings to the cutting surface of the tool.

As stated above, such polymeric replicas of the original masterstructure again can be used to produce 2^(nd), 3^(rd) or highergeneration replicas (“sub-masters”) which have either the same reliefstructure as the original master or a negative of it. Crucial is thatthe final microcutting tool comprises sharp protruding edges, such assharp ridges. In order to produce such “submasters” via e.g. embossing,injection- or reactive moulding, which subsequently can be used toreplicate the final microcutting tool, preferably polymeric materialsare employed that display good non-adhesive properties, such asperfluorinated polymers, polyolefins, polystyrene, or silicone rubbers(e.g. polydimethylsiloxane). Obviously, such submasters may be bended orrolled or shaped in whatever geometry is most desired depending on thedevice and device configuration to be fabricated in order to producecylinder-shaped microcutting tools or microcutting tools of more complexgeometries. For this purpose, it is useful to use flexible, polymericmaterials, such as polydimethylsiloxane or polyolefins for submasterproduction.

Submasters according to one embodiment of the present invention wereprepared by first producing a negative replica in polystyrene, PS(atactic polystyrene, M_(w)≈105 kg mol⁻¹, T_(g)≈100° C.; Aldrich). Forthis purpose, PS granulates were embossed at 180° C. with a siliconmaster comprising sharp grooves (height h≈10 mm, periodicity Λ=500 mm,edge angle α=70°; MikroMasch, Narva mnt. 13,10151, Tallinn, Estonia),applying onto the latter a nominal pressure of 300 g mm⁻² for 5 min (cf.Stutzmann, N., Tervoort, T. A, Bastiaansen, C. W. M. Feldman, K & Smith,P. Adv. Mater. 12, 557 (2000)). Subsequently, 2^(nd) generationpolydimethylsiloxane (Sylgard silicone elastomer 184; Dow CorningCorporation) replicas according to one embodiment of the presentinvention were fabricated by poring the pre-polymeric liquid onto theseembossed PS films and curing it for 24 hours at room temperature in airatmosphere. The final microcutting tools were fabricated by producing a3^(rd) generation thermoset replica by first melting the cyanate esterresin Primaset PT15 (Lonza) at 110° C. for 30 min, casting this meltonto the structured PDMS films, curing it for 4 hours at 170° C. and,subsequently for 24 hours at 200° C., and removing at the end the PDMSreplicas from the cured, surface-structured thermoset.

It is also possible to use microcutting tools fabricated by anisotropicetching directly from thin crystalline wafers. If the wafer thickness isless than 50 μm such microcutting tools are flexible and can be mountedon a cylindrical roller suitable for reel-to-reel embossing.

In order to fabricate complex integrated circuits using microcutting themicrocutting tool might be fabricated with an arbitrary pattern ofwedges, that is able to define the critical device dimensions of anarbitrarily complex circuit. If such a complex master is defined byanisotropic etching of a crystalline wafer, sophisticated etchingtechniques such as corner compensation (cf. van Kampen, R. P. andWolffenbuttel, R. F. J. Micromech. Microeng. 5, 91 (1995), Scheibe, C.and Obermeier, E. J. Micromech. Microeng. 5, 109 (1995), Enoksson, P. J.Micromech. Microeng. 7, 141 (1997)) need to be used in order to ensurethat all protruding wedges of the tool that are supposed to cut acertain layer of the multilayer stack have the same height.

Alternatively, the microcutting tool may have a very simple wedgepattern, such as an array of parallel, linear wedges. In this case allcritical device dimensions need to be layout on a regular grid. However,circuits of arbitrary complexity can still be defined by appropriatelydefining the coarse pattern of the layer to be cut, and by depositingappropriate interconnections between the regularly spaced devices. Thisprocess is particularly suited for a reel-to-reel process based on acombination of direct printing and microcutting (see FIG. 12) In a firststep a regular array of source-drain electrodes with suitableinterconnections are written by a technique such as inkjet printing.Then the channel gap between source-drain electrodes is defined bymicrocutting. An active matrix display is an example where such aregular array of TFTs is particularly useful.

Similar approaches can be applied to the fabrication of via-holes formultilayer interconnect schemes starting from a microcutting tool with aregular array of point like protrusions with subsequent filling ofselected via holes to provide the desired circuit function.

Another example demonstrates a method by which features in differentlayers of the device can be cut selectively by defining wedges ofdifferent height on the same master. The etching process to define thewedges of the master can be performed in subsequent steps to defineseveral patterns of wedges with different heights, for example byvarying the width of the lithographic features of the etch mask. Such amaster is useful to define critical device dimensions in several layersof the device in a single embossing step.

The tool preferably has a cutting face that is presented to the materialto be cut, and from which the cutting protrusions protrude. The cuttingface is preferably planar. In many situations it will be preferable thatthe cutting protrusions all have the same depth.

The processes and devices described herein are not limited to devicesfabricated with solution-processed polymers. Some of the conductingelectrodes of the TFT and/or the interconnects in a circuit or displaydevice (see below) may be formed from inorganic conductors, that can,for example, be deposited by printing of a colloidal suspension or byelectroplating onto a pre-patterned substrate. In devices in which notall layers are to be deposited from solution one or more PEDOT/PSSportions of the device may be replaced with an insoluble conductivematerial such as a vacuum-deposited conductor.

For the semiconducting layer any solution processible conjugatedpolymeric or oligomeric material that exhibits adequate field-effectmobilities exceeding 10⁻³ cm²/Vs, preferably exceeding 10⁻² cm²/Vs, maybe used. Suitable materials are reviewed for example in H. E. Katz, J.Mater. Chem. 7, 369 (1997), or Z. Bao, Advanced Materials 12, 227(2000). Other possibilities include small conjugated molecules withsolubilising side chains (J. G. Laquindanum, et al., J. Am. Chem. Soc.120, 664 (1998)), semiconducting organic-inorganic hybrid materialsself-assembled from solution (C. R. Kagan, et al., Science 286, 946(1999)), or solution-deposited inorganic semiconductors such as CdSenanoparticles (B. A. Ridley, et al., Science 286, 746 (1999)).

The semiconducting material can also be an inorganic semicondcutor suchas thin film silicon deposited by vacuum or plasma depositiontechniques.

The electrodes may be coarse-patterned by techniques other than inkjetprinting. Suitable techniques include soft lithographic printing (J. A.Rogers et al., Appl. Phys. Lett 75, 1010 (1999); S. Brittain et al.,Physics World May 1998, p. 31), screen printing (Z. Bao, et al., Chem.Mat. 9, 12999 (1997)), and photolithographic patterning (see WO99/10939) or plating. Ink-jet printing is considered to be particularlysuitable for large area patterning with good registration, in particularfor flexible plastic substrates.

The device(s) can be deposited onto another substrate material, such asPerspex or a flexible, plastic substrate such as polyethersulphone. Sucha material is preferably in the form of a sheet, is preferably of apolymer material, and may be transparent and/or flexible.

Although preferably all layers and components of the device and circuitare deposited and patterned by solution processing and printingtechniques, one or more components such as a semiconducting layer mayalso be deposited by vacuum deposition techniques and/or patterned by aphotolithographic process.

Devices such as TFTs fabricated as described above may be part of a morecomplex circuit or device in which one or more such devices can beintegrated with each other and or with other devices. Examples ofapplications include logic circuits and active matrix circuitry for adisplay or a memory device, or a user-defined gate array circuit.

The microcutting process may be used to pattern other components of suchcircuit as well. One possibility is patterning of the pixel electrodesof an active matrix display. In a high-resolution display the opticalstate of each pixel (liquid crystal, organic or polymer light emittingdiode, for example) is controlled by the voltage applied to each of thepixel electrodes. In an active matrix display each pixel contains avoltage latch, such as a TFT, which holds the voltage on the pixel whilethe other pixels are addressed and written. If the TFTs and addressinglines are in a different layer of the device as the pixel electrodes,for example, located below the pixel electrode and connected with thepixel electrode through a via hole, microcutting of a continuous pixelelectrode can result in very high aperture ratio display, in which theaperture ratio is limited only by the small width of the microcutgrooves.

It may be advantageous to hold the microcutting tool at the sametemperature as the multilayer structure during the forcing step, e.g.within 5 C. Alternatively, they may be at different temperatures: thusthe temperature of the microcutting tool may be more than 5° C.different from the temperature of the multilayer structure during theforcing step.

The present invention is not limited to the foregoing examples. Aspectsof the present invention include all novel and/or inventive aspects ofthe concepts described herein and all novel and/or inventivecombinations of the features described herein.

The applicant draws attention to the fact that the present inventionsmay include any feature or combination of features disclosed hereineither implicitly or explicitly or any generalisation thereof, withoutlimitation to the scope of any definitions set out above. In view of theforegoing description it will be evident to a person skilled in the artthat various modifications may be made within the scope of theinventions.

1. A method for forming an electronic switching device in a multi-layerstructure comprising at least a first layer and an underlying secondlayer, the method comprising: forcing a microcutting protrusion of acutting tool into the multi-layer structure so as to cause theprotrusion to microcut through the first layer and into the secondlayer; and wherein the microcut first layer forms at least one electrodeof said electronic switching device, wherein the second layer is in thesolid state while the forcing step is performed, and wherein theelectronic switching device comprises a semiconducting material betweensource and drain electrodes, and wherein the microcutting serves todefine an edge adjacent to the semiconducting material of at least oneof said source and drain electrodes.
 2. The method as claimed in claim1, wherein the first and second layers have different electricalproperties.
 3. The method as claimed in claim 1, wherein the material ofwhich at least one layer is formed is in its solid state while theforcing step is performed.
 4. The method as claimed in claim 1, whereinthe protrusion has at least one edge having a radius of curvature lessthan 100 nm.
 5. The method as claimed in claim 1, wherein the protrusionhas at least one edge having a radius of curvature less than 10 nm. 6.The method as claimed in claim 1, wherein the depth of the protrusion isless than 10 micrometers.
 7. The method as claimed in claim 1, whereinthe depth of the protrusion is less than 1 micrometers.
 8. The method asclaimed in claim 1, wherein the width of the protrusion in at least onedirection parallel to the layers is less than 100 micrometers.
 9. Themethod as claimed in claim 1, wherein the width of the protrusion in atleast one direction parallel to the layers is less than 10 micrometers.10. The method as claimed in claim 1, wherein the width of theprotrusion in at least one direction parallel to the layers is less than2 micrometers.
 11. The method as claimed in claim 1, wherein theprotrusion is formed of a material whose surface has been treated toreduce the coefficient of friction between the tool and multilayerstructure.
 12. The method as in claim 1 in which the microcutting toolor the multilayer structure or both are in contact with a soft materialduring the micro cutting step.
 13. The method as claimed in claim 1,wherein the tool is a flexible sheet bearing the protrusion.
 14. Themethod as claimed in claim 1, wherein the tool is rolled over thestructure.
 15. The method as claimed in claim 1, wherein the tool isrolled over the structure in substantially linear path.
 16. The methodas claimed in claim 1, wherein the cutting tool has a plurality ofmicrocutting protrusions.
 17. The method as claimed in claim 16, whereinthe protrusions take the form of elongated ridges.
 18. The method asclaimed in claim 17, wherein the ridges are linear.
 19. The method asclaimed in claim 17, wherein the ridges are parallel.
 20. The method asclaimed in claim 16, wherein the protrusions are all of the same depth.21. The method as claimed in claim 16, wherein the protrusions are ofdifferent depth.
 22. The method as in claim 1, wherein the temperatureof the microcutting tool is within 5° C. of the temperature of themultilayer structure during the forcing step.
 23. The method as in claim1, wherein the temperature of the micro cutting tool is more than 5° C.different from the temperature of the multilayer structure during theforcing step.
 24. The method as claimed in claim 1, wherein the secondlayer is electrically non-conductive or semiconductive.
 25. The methodas claimed in claim 1, wherein the first and second layers formfunctionally different parts of the electrical device.
 26. The method asclaimed in claim 1 wherein the microcut first layer forms a plurality ofelectrodes of the electronic switching device.
 27. The method as claimedin claim 1 wherein the microcut layer forms source and drain electrodesof a transistor device.
 28. The method as claimed in claim 1, whereinthe multi-layer structure has additional layers on the other side of thesecond layer from the first layer, and the step of forcing comprisesforcing the microcutting protrusion of the cutting tool into themultilayer structure so as to cause the protrusion to microcut throughthe first layer, and the second layer, and through or into at least oneof the additional layers.
 29. The method as claimed in claim 28, whereinat least one of the additional layers is electrically conductive orsemiconductive.
 30. The method as claimed in claim 29, wherein themicrocutting tool cuts into or through the said additionalsemiconductive or conductive layer.
 31. The method as in claim 28,wherein the first layer and said additional conductive or semiconductivelayer form functionally different elements of the device.
 32. The methodas in claim 31, wherein said additional conductive or semiconductivelayer form electrodes of an electronic switching device.
 33. The methodas in claim 32, wherein the first layer and said additional conductiveor semiconductive layer form source and drain electrodes, respectively,of a transistor device.
 34. The method as claimed in claim 1, whereinthe step of forcing forms at least one recess in the structure, and themethod comprises depositing at least one or more materials on top of themicrocut multilayer structure.
 35. The method as claimed in claim 34,wherein at least one of the said materials is deposited selectively intothe recess or selectively adjacent to the recess or selectively adjacentand partly into the recess.
 36. The method as claimed in claim 34,wherein at least one of the said materials deposited over the multilayerstructure forms a conformal coating on the multilayer structure orselectively on the recess structure or selectively on at least part ofthe structure adjacent to the recess.
 37. The method as claimed in claim34, wherein at least one of the said materials is deposited by printing.38. The method as claimed in claim 34, wherein at least one of saidmaterials is a semiconductive material.
 39. The method as claimed inclaim 38, wherein said semiconductive material is a polymer.
 40. Themethod as claimed in claim 38, wherein said semiconductive materialforms an active semiconducting layer of the electronic switching device.41. The method as claimed in claim 38, wherein said semiconductivematerial is arranged to emit light.
 42. The method as claimed in claim34, wherein at least one of the materials deposited into the recess isarranged to guide light.
 43. The method as claimed in claim 34, whereinone of said materials deposited into the recess is electricallyconductive.
 44. The method as claimed in claim 43, wherein saidconductive material forms the gate electrode of the electronic switchingdevice.
 45. The method as in claim 34, wherein at least one of thematerials deposited onto the multilayer structure is patterned.
 46. Themethod as in claim 34, wherein at least one of the materials depositedonto the multilayer structure is patterned by direct printing.
 47. Themethod as claimed in claim 1, wherein the first layer is organic. 48.The method as claimed in claim 1, wherein the first layer is metallic.49. The method as claimed in claim 1 wherein the second layer isorganic.
 50. The method as claimed in claim 1, wherein the electronicswitching device is a transistor.
 51. The method as claimed in claim 1,comprising a second step of forcing the microcutting protrusions of thesame or a different cutting tool into the multilayer structure whereinduring the second step of forcing the cutting tool is orientateddifferently from the orientation of the cutting tool during the firststep of forcing.
 52. The method as claimed in claim 51 wherein the firststep of forcing forms a first series of elongate cuts in the structure,and the second step of forcing forms a second set of elongate cutsangled with respect to the first set of cuts.
 53. The method as in claim1, wherein at least one of the layers of the multilayer structure ispatterned.
 54. The method as claim 1, wherein at least one of the layersof the multilayer structure is patterned by direct printing.
 55. Themethod as in claim 1 wherein the multilayer structure also includes asubstrate and the microcutting protrusion microcuts through the firstlayer without microcutting completely through the substrate.
 56. Themethod as in claim 1 wherein said forcing is carried out by embossing.57. The method as claimed in claim 1, wherein the forcing of themicrocutting protrusion is done without lateral movement of theprotrusion with respect to the multilayer structure, and wherein themethod further comprises withdrawing the microcutting protrusion so asto leave a recess having a size determined by the shape of themicrocutting protrusion and the depth to which it is forced in to themultilayer structure; and wherein the second layer comprises a materialdifferent from the material of said first layer.
 58. The method asclaimed in claim 1, wherein the method further comprises withdrawing themicrocutting protrusion so as to leave a recess having a size determinedby the shape of the microcutting protrusion and the depth to which it isforced in to the multilayer structure such that all dimensions of therecess are determined by the shape of the microcutting protrusion andthe depth to which it is forced onto the multilayer structure; andwherein the second layer comprises a material different from thematerial of said first layer.